Technical Field
The disclosure relates generally to checking of the integrity of a communication between two circuits, and such as checking of the integrity of the data that are read and written by a bus from/to a memory of DDR type.
Description of the Related Art
FIG. 1 is a block diagram of a system implementing a memory of DDR (Double Data Rate) type. The DDR memory is connected to a circuit, for example a system on a chip SoC, by a standardized memory bus B. The SoC circuit and the DDR memory are each connected to the bus B by an address interface A, a data interface D and a control interface CTRL.
In the DDR memory, the interfaces allow access to a memory map MEM that can be associated with an error connection circuit ECC. The address interface A is designed to receive one-way addresses through the bus B, addresses that can be used to select memory cells both in read mode and in write mode. The data interface D is bidirectional—it receives from the bus B data to be written to the memory and produces them through a W channel, and it receives on an R channel data that have been read from the memory and transmits them on the bus. Since the read and write operations in the DDR memory are not concurrent, the data are able to travel through the same lines of the bus B. The control interface CTRL conveys various signals entering and leaving through respective channels W and R.
More detailed information about DDR memory interfaces can be found in the JEDEC standards.
The A, D and CTRL interfaces of the SoC circuit have functions that are symmetrical with respect to the interfaces of the memory.
In some applications (e.g., safety applications), the hope is to guarantee the integrity of the data interchanged with a memory. To this end, redundancy solutions are frequently used that can considerably increase the silicon surface area of the circuits. When standardized components are used, such as DDR memories, the redundancy is often obtained by doubling the number of memories in order to store the data with a copy.